The desire for integrated circuits of greater complexity and performance has driven designers to shrink the size of minimum features in the horizontal plane. Avoidance of excessive current density, however, has meant that the horizontal scaling has not necessarily been accompanied by a reduction in the vertical dimension. This has resulted in increase of the ratio of feature height to feature width, something generally referred to as aspect ratio. The increased aspect ratio has resulted in problems with the use of conventional single-layer resists in integrated circuitry fabrication. Multilevel resist processes have been developed to overcome these problems.
Multilevel resist processing is a lithography method (not necessarily photolithography) whereby a thick base layer (not necessarily a resist sensitive layer) is covered with one or more thinner layers, the top one of which is a sensitive film at the wavelength of light or other exposure energy to be used. The thick base layer is typically an organic layer which is spun onto the wafer and may be thicker than the underlying steps to provide an outer surface which is smooth and generally planar. If the underlaying layer over which the base layer is provided is not already planar, the base layer is typically intended to provide a significantly more planar outer surface than the original wafer topography. An example thickness for the base layer is 1 micron.
After baking this bottom layer, a thinner imaging layer is provided thereover. In certain instances, a thin intermediate masking layer, such as SiO.sub.2, is deposited on the thick layer prior to depositing the imaging layer. High resolution patterns are then created in the thin top layer through openings in a mask utilizing incident energy capable of changing properties of the exposed portions of the outer layer. The transformed regions of the thin top layer are then removed. The removed portions are next precisely transferred into the underlying layers, including the thick planarizing layer, using the delineated imaging layer as a blanket exposure or etching mask to pattern the base or planarizing layer. Example preferred prior art methods include reactive ion etching utilizing an oxygen-containing gas in a high density plasma etcher for the base layer. For the intermediate masking layer, an example etching chemistry is a fluorocarbon/hydrofluorocarbon gas mix.
Multilevel resist technology has not gained significant popularity due to the added complexity and cost compared to standard lithography/resist combinations using a single layer of resist. Yet there are at least two reasons that may make the use of multilevel resist technologies for patterning substrates more desirable in the future.
First, shorter and shorter wavelengths when the resist layer is photoresist are being utilized to achieve better resolution. Unavailability of appropriate single layer resists for the wavelength of interest may prevent use of single layer resist. For example, production wavelengths below 200 nanometer may fundamentally require use of multilevel resist technology. Second, multilayer resist technology may be utilized to extend the useful life of current lithography tools by decreasing the imaging layer thickness. This would be highly desirable to avoid or delay incurring the very high cost of purchasing new lithography technology and equipment.
However, the use of multilevel resist technology to define very small feature sizes (i.e., less than or equal to 2000 Angstroms) has proven to be difficult as the reactive ion etching processes currently in use produce two undesirable and competing side effects. For example, consider the problem with respect to the prior art constructions depicted by FIGS. 1 and 2. FIG. 1 illustrates a semiconductor wafer fragment 10 comprising a bulk monocrystalline silicon substrate 12 having exemplary conductive features in the form of lines 14 patterned thereover. A planarizing layer 16 of insulating dielectric material is provided over substrate 12 and lines 14. The goal or intent in this example is to etch a contact opening to each of lines 14. A thick base layer 18 (i.e., 10,000 Angstroms thick) of insulative organic polymer is provided over layer 16. An intermediate hard mask layer 20, for example SiO.sub.2, is provided over layer 18, and a top layer 22 of desired energy sensitive material is provided over layer 20. Layer 22 is illustrated as having been exposed through a mask and subsequently developed to form openings 24 therethrough to layer 20.
Referring to FIG. 2, the substrate is next etched (for example using a fluorocarbon/hydrofluorocarbon gas mix) to extend openings 24 through layer 20. Then, the substrate is reactive ion etched (typically utilizing some gas containing oxygen) to etch through layer 18. Example reactive ion etching gases include O.sub.2, O.sub.2 and N.sub.2, CO.sub.2 and N.sub.2 O. The reactive ion etching with the oxygen species has the effect of transferring the opening patterning through hard mask layer 20, and etches downwardly through base layer 18. It also completely etches away the overlying masking layer 22. FIG. 2 illustrates two competing adverse effects which can occur with such etching. First, unfortunately the high energy which is desired to achieve a suitable etch rate in the reactive ion etching can have a tendency to facet etch silicon dioxide layer 20, as evidenced by the outwardly flaring nature of the formed openings within layer 20. This can result in eventually widening the subject openings to the point where adverse effects are achieved in the desired pattern.
One prior art technique for reducing this problem is to lower the energy in the reactive ion etching. Yet, energy lowering reduces etch rate. Also unfortunately, the energy lowering has a tendency to result in poor profile control caused by distortion of the lower energy ions as they travel through the feature towards its bottom. Specifically, the negatively charged electrons tend to charge the upper portion of the feature with a negative charge. This causes the lower energy positive ions to be deflected. This deflection reduces the anisotropy of the etch, leading to distortion of the etch profile from the desired vertical shapes. The distortion results from the charge buildup on the insulating sidewall of the etching feature in layer 18.
It would be desirable to overcome these problems associated with multilayer resist and other processing in fabricating semiconductor wafers.